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Addressing resource contention and timing predictability for multi-core architectures with shared memory interconnects

Wang, H., Audsley, N. C. ORCID: 0000-0003-3739-6590 and Chang, W. (2020). Addressing resource contention and timing predictability for multi-core architectures with shared memory interconnects. Paper presented at the 2020 IEEE Real-Time and Embedded Technology and Applications Symposium, 21-24 Apr 2020, Sydney, Australia.

Abstract

Multi-core architectures are increasingly being used in real-time embedded systems. In general, such systems have more processors than the shared memory modules, potentially causing severe interference over memory accesses. This resource contention could lead to substantial variation on memory access latencies, and thus wide fluctuation in the overall system performance, which is highly undesirable especially for the time-critical applications. In this paper, we address resource contention and timing predictability for multi-core architectures with distributed memory interconnects. We focus on the locally arbitrated interconnect constructed by pipelined multiplexing stages with local arbitration, while the globally arbitrated interconnect employing global scheduling to the same architecture potentially suffers synchronisation issue and requires strict coordination. Our contributions are mainly threefold: (i) We analyse the resource contention across the memory access data path, and report the accurate calculational method to bound the worst-case behaviour. (ii) We compare the average-case behaviour of the locally arbitrated and the globally arbitrated architectures with experiments, demonstrating varying memory latencies caused by the resource sharing issue. (iii) We propose an architectural modification to smooth resource sharing. Evaluations on simulators and FPGA implementations with synthetic memory workload show that the latency variation is significantly reduced, contributing towards timing predictability of multi-core systems.

Publication Type: Conference or Workshop Item (Paper)
Additional Information: © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Publisher Keywords: field programmable gate arrays; interconnections; memory architecture; multiprocessing systems; shared memory systems
Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Departments: School of Mathematics, Computer Science & Engineering
Date available in CRO: 04 Nov 2021 14:31
Date deposited: 4 November 2021
Date of acceptance: 10 June 2020
Date of first online publication: 10 June 2020
URI: https://openaccess.city.ac.uk/id/eprint/26986
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