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A queuing network model for multi-programming computer systems

Al-Akabaoui, M. S. (1977). A queuing network model for multi-programming computer systems. (Unpublished Doctoral thesis, The City University)

Abstract

In mltiprogramming computer systems, programs request service of central processor or peripheral processor(s) during execution. In the case of the peripheral processor requests, a hierarchic sequence of events is followed while servicing them. This sequence is manifested by the requests issued to the channel processors, peripheral control units and the peripheral devices themselves. The hierarchic sequence can be represented by service despatching in a structure of service stations in a queueing network. The higher level service stations in this class of networks control and monitor the operations in the lower level service stations. Each service station in the respective level may render part of the service for a particular program request and despatches the request to other stations connected to it in the lower levels for continued service. The highest service station(s) in these networks corresponds to the CPU class of processor(s), whilst the lowest stations correspond to the peripheral device class of processors.

In this research, the steady state analysis for this class of structured networks is undertaken. The analytical solution in both closed and open form networks is obtained. The developed solution is then considered in a case study of an interactive computer system. To evaluate the stochastic parameters required in the solution, the interactive user behavioural characteristics are first studied by a statistical analysis of real-life working conditions. The computer system considered in the case study is then examined in relation to the processor specifications, the hardware architectural features and the software characteristics.

A simulation is developed to apply the analytical method to closed form network environment. The resulting performance measures are examined and the bottleneck areas, which degrade the system performance, are identified. Methods of improving the system performance by varying the processor specifications and the hardware architecture are investigated. The algorithms for the software procedures which contribute to an even distribution of the workload on the bottleneck processors are then developed. The limitations in implementing the devised algorithms are considered and the methods of carrying out these software changes in the system are described.

Publication Type: Thesis (Doctoral)
Subjects: Q Science > QA Mathematics
Departments: School of Science & Technology > Department of Mathematics
School of Science & Technology > School of Science & Technology Doctoral Theses
Doctoral Theses
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