City Research Online

Abstract

This thesis is concerned with the test generating procedures for logic circuits using a "black-box" approach. By a black-box approach it is meant that the internal probing of a circuit is not permitted.

The project is divided into two phases : development of new procedures for diagnosing permanent faults and the use of these procedures for detecting intermittent faults. The basis of the “procedures is the 'Fault-folding' concept, which is used to form fault equivalence classes for a given combinational circuit by "folding" faults towards the primary inputs.

An algorithm is presented for finding a minimal set of tests for the detection and location of single and multiple faults in a combinational logic network.

Synchronous sequential circuits in a particular state behave like a combinational circuit with feedback paths acting as primary inputs. Fault-folding is used to find the minimum number of states at which the circuit is to be tested, to test cover all faults in the circuit. A checking sequence is then developed to test the circuit at the required states, thus taking into account both behaviour and structure of the network. A fault-location procedure is suggested which locates faults within an equivalent class.

Fault detection procedures for asynchronous sequential circuits are also described. Asynchronous circuits are transformed into synchronous circuits and tests are generated for these versions of the circuits.

Finally a procedure, based on probability theory, is developed to detect a well-behaved intermittent fault in a logic network. The procedure employs repeated applications of a test or a test sequence. The time-period, during which a test or test sequence is repeatedly applied, depends on the probability of detection desired and is derived from the Poisson distribution.

Algorithms described in the thesis are computer-programmed using FORTRAN IV; computational results are reported.

The programme used for automatic test generation of combinational circuits can handle circuits having up to 15 primary inputs, 10 primary outputs and 95 basic gates. The corresponding programme for synchronous sequential circuits is applicable to circuits is having up to 50 gates and 16 internal states.

The main objective in developing the programmes in the thesis, is to prove that the algorithms described are suitable table for computer-programming; no particular emphasis has been placed on the efficiency of the resulting software.

Publication Type:	Thesis (Doctoral)
Subjects:	Q Science > QA Mathematics > QA76 Computer software T Technology > T Technology (General) T Technology > TK Electrical engineering. Electronics Nuclear engineering
Departments:	School of Science & Technology > Department of Engineering School of Science & Technology > School of Science & Technology Doctoral Theses Doctoral Theses

Export

Downloads