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Analogue hardware based algorithm for low-power and low-voltage position measurement systems with enhanced resolution

Leitis, K. (2004). Analogue hardware based algorithm for low-power and low-voltage position measurement systems with enhanced resolution. (Unpublished Doctoral thesis, City, University of London)


Position measurement systems are used in a wide variety of applications based on different sensing principles. Whatever the application or sensing method, they all share common issues of accuracy, robustness and power consumption. This thesis concentrates on two aspects of sensor interface design in order to achieve a very low power consumption for position measurement systems, in order to optimise their use for battery applications.

A new architecture and optimized components have been investigated with regard to low power and low voltage operation. The architecture establishes typical properties of position measurement systems such as linearization and resolution enhancement. A new method for resolution enhancement in respect of low power and low voltage system requirements is proposed within this work. The same major requirements are also fulfilled on a component level.

On an architectural level, the method utilizes signal symmetry provided by the sensor signal. A very common output signal of position measurement sensor elements establishes a sine and a cosine waveform. With folding and signal transformation techniques these signals are coarse converted and pre- processed before A/D conversion. As a result, the number of components is reduced and a significant amount of power is saved.

Many position measurement systems linearize the sensor element signals by digital computation. This work proposes a method of linearization within the A/D converter. The advantage is that no extra power consumption is involved because no additional elements are inserted into the A/D converter. By using a non-linear resistor network that composes the sine and cosine sensor signal, a linearized output is obtained. As a result the linearization algorithm is realised by an analogue hardware circuit. This has the added benefit of reducing the circuit noise, a common problem with digital circuits.

In addition to the architectural level design, new components realized as integrated circuit cells, contribute to a reduction of the overall power consumption. Both, the power supply voltage and the power supply current are significantly reduced. A trade-off between performance and reduction of

power consumption has been the basis of the circuit design. Circuit components that determine the minimum power supply voltage have been the subject of a thorough investigation in respect of sub-threshold or moderate inversion operation. As a result, a power supply voltage range smaller than given by the fundamental limits for strong inversion operation can be chosen. These components were realized as a physical cell design and implemented in the form of a test chip. Test results are reported that demonstrate the practical performance of the overall architecture and individual components.

A new error model has been developed for the overall sensor system in order to investigate the influence of parameter deviation and inherent errors. The model has been used in simulation studies that demonstrate the overall accuracy and robustness of the design.

The thesis concludes with a summary of the major achievements and an evaluation, in the form of a comparison with existing systems.

Publication Type: Thesis (Doctoral)
Subjects: T Technology > TJ Mechanical engineering and machinery
T Technology > TK Electrical engineering. Electronics Nuclear engineering
Departments: School of Science & Technology > Engineering > Electrical & Electronic Engineering
School of Science & Technology > School of Science & Technology Doctoral Theses
Doctoral Theses
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