City Research Online

Abstract

This brief presents and evaluates a pre-coding algorithm to reduce power consumption and improve data retention in NAND-based solid-state drives. Compared to the state-of-the-art asymmetric coding and stripe pattern elimination algorithm, the proposed write pattern format algorithm (WPFA) achieves better data retention while consuming less power. The hardware for WPFA is simpler and requires less circuitry. The performance of WPFA is evaluated by both computer simulations and field-programmable gate array implementation.

Publication Type:	Article
Additional Information:	© 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Publisher Keywords:	Solid-state drive, reliability, NAND flash memory, power consumption
Subjects:	Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Departments:	School of Science & Technology > Engineering
SWORD Depositor:	Symplectic Administrator

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