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Abstract

Digital Signal Processing (DSP) has a number of well known advantages compared with analogue signal processing. Its main drawback of complexity is becoming more manageable with the advent of VLSI systems. The digital filter is an important DSP function which has wide application and plays some part in most DSP systems. The practicality of DSP is therefore dependent on the efficient implementation of digital filters with VLSI systems. The aim in this thesis is to design architectures for this purpose with an emphasis on identifying features of structures which can be exploited in the design of efficient architectures.

The first step towards this goal is the selection of suitable digital filter structures. This issue is addressed from the viewpoints of finite wordlengths and hardware implementation. Appropriate measures are introduced and used to assess the suitability of a number of structures from the literature ; direct form II, cascaded second order sections, parallel second order sections, Gray-Markel normalized ladder, cascaded unit elements WDF, lattice WDF, LC ladder WDF and IVR generalized WDF. It is shown that of these, the cascaded unit elements WDF and the lattice WDF are best suited to VLSI implementation.

A novel finite wordlength design program for cascaded unit elements WDFs is presented. This program is based on a heuristic approach and exploits a number of properties of cascaded unit elements WDFs which have been identified. Also, programs for the design of lattice WDFs based on cascaded unit elements and LC networks are given.

An architecture for the cascaded unit elements WDF is given which exploits the inherent parallelism of the structure to optimize the speed in a multiplexed scheme. This is achieved by pipelining the basic section. Architectures for lattice WDFs based on cascaded unit elements and all-pass sections are also presented. Simple modifications to the structure, multiplexing and pipelining are used to optimize efficiency.

The relationship between a theoretical discrete system and its synchronous digital realization is explored. This is used to show that synchronous digital realizations of WDFs based on unit elements can be used to process two signals simultaneously without requiring any modifications. It is necessary for the two signals to be skewed by half the sampling period.

This property is exploited in the design of a reconfigurable, programmable architecture which can be used to implement two separate UEWDFs, two UEWDFs in cascade or a lattice WDF. Appropriate results are given to demonstrate the efficiency and versatility of this architecture. Similar ideas are used to design an architecture capable of implementing two separate LC ladder WDFs, two LC ladder WDFs in cascade or a lattice WDF.

Closing arguments are given to show that the work presented in this thesis may be used in the development of a CAD system for the VLSI implementation of digital filters which is based on a standard cell approach.

Publication Type:	Thesis (Doctoral)
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering
Departments:	School of Science & Technology > Department of Engineering School of Science & Technology > School of Science & Technology Doctoral Theses Doctoral Theses

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